M
N
progIn
reset
progLoad
start
result
clk
valid
done
output
0-7
0-3
4-7
pRAM
str
C
ld
1A
1Din
2A
1D
2D
RAM
rRAM
str
C
ld
1A
1Din
2A
1D
2D
RAM
input
M
N
progIn
reset
progLoad
start
result
clk
clk
Q4
D
C
Q
Q
D
clk
Q3
D
C
Q
Q
D
clk
Q2
D
C
Q
Q
D
clk
Q1
D
C
Q
Q
D
clk
Q0
D
C
Q
Q
D
clk
0
1
2
3
4
0-4
statecurrent
Q4
Q3
Q2
Q1
Q0
Q0
Q1
Q2
Q3
Q4
0
0
0
0
0
statecurrent
statecurrent
statecurrent
statecurrent
statecurrent
00000 start
00001 fetch
00010 decode
00011 writeA
00100 writeB
00101 writeC
00110 writeD
00111 rRAM[operand]
01000 ALU
01001 CMP
01010 isPrime
01011 reminder
01100 load rRAM[7:4]
01101 writeB
01110 writeD
01111 writeA
10000 write flag
10001 write EQ
10010 write EQ
10011 load rRAM[3:0]
10100 calc LCM
10101 write rRAM
10110 write rRAM
10111 jmp
11000 reset
11001 factorial
11010 max
11011 -
11100 -
11101 halt
11110 result
11111 done
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
start
0
0
0
1
0
a
b
ci
s
co
Add
0
D
C
en
Q
Reg
1
clk
0
selPC
operand
loadPC
PC
pRAMaddress
en
C
clr
out
ovf
Counter
progLoad
clk
progIn
clk
reset
address
address
progLoad
instruction
1
pRAMaddress
pRAM[operand]
pRAM
output
reg
accA
D
C
en
Q
Reg
clk
accB
D
C
en
Q
Reg
clk
regC
D
C
en
Q
Reg
regD
D
C
en
Q
Reg
clk
clk
0
operand
accB
regC
regD
pRAM[operand]
rRAM[operand]
ALU
0
0
operand
accA
regD
0
0
accA
M
N
0
0
accA
M
N
0
selA
selB
selC
selD
loadA
loadB
loadC
loadD
accA
accB
regC
regD
flag
comp
a
b
>
=
<
accA
accB
primelist
A
sel
D
ROM
accA
1
reminder
a
b
>
=
<
a
b
q
r
Div
accA
accB
0
>
D
C
en
Q
Reg
=
D
C
en
Q
Reg
<
D
C
en
Q
Reg
clk
clk
clk
0
0
sel=
load=
load>
load<
>
=
<
0
operand
E
F
selrRAMaddress
0
accA
operand[3:0]
operand[7:4]
LCM1
LCM2
0
selrRAM
loadrRAM
operand
rRAM[operand]
rRAM
a
b
ci
s
co
Add
accA
accB
0
A+B
accA
accB
0
A-B
a
b
ci
s
co
Sub
accA
accB
A*B
a
b
mul
Mul
a
b
q
r
Div
accA
accB
A/B
A%B
accA
!A
AandB
accA
accB
accA
accB
AorB
accA
accB
AxorB
in
shift
out
Shift
accA
accB
A<<B
in
shift
out
Shift
accA
A<<<B
in
shift
out
Shift
accA
A>>B
in
shift
out
Shift
accA
A>>>B
ALU
0-7
0-3
4-7
accB
0-7
0-3
4-7
accB
0-7
0-3
4-7
accB
0-7
0-3
4-7
0
selALUops
A+B
A-B
A*B
A/B
A%B
!A
AandB
AorB
AxorB
A<<B
A<<<B
A>>B
A>>>B
AB
ALU
0
0
statecurrent
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A2
loadPC
A3
loadA
A15
loadB
A4
A13
loadC
A5
loadD
A6
A14
loadrRAM
A7
A22
load=
A16
A18
A17
load>
load<
A16
A16
0-13
0-7
8-13
instruction
operand
opcode
instruction
D
C
en
Q
Reg
clk
loadinstruction
loadinstruction
0
opcode
op0
op1
op2
op3
op4
op5
op6
op7
op8
op9
op10
op11
op12
op13
op14
op15
op16
op17
op18
op19
op20
op21
op22
op23
op24
op25
op26
op27
op28
op29
op30
op31
op32
op33
op34
op35
op36
op37
op38
op39
op40
op41
op42
op43
op44
op45
op46
op47
op48
op49
op50
op51
op52
op53
op54
op55
op56
op57
op58
op59
op60
op61
op62
op63
selA
selB
selD
A
sel
D
ROM
1
opcode
A
sel
D
ROM
1
opcode
A
sel
D
ROM
1
opcode
A
sel
D
ROM
1
opcode
A
sel
D
ROM
1
opcode
sel=
selrRAM
A
sel
D
ROM
1
statecurrent
selrRAMaddress
A
sel
D
ROM
1
statecurrent
selALUops
opcode
0-5
0-3
4,5
loadLCMa
A12
A19
loadLCMb
nextstatedecode
A
sel
D
ROM
1
opcode
decode
decode
0-4
0
1
2
3
4
decode0
decode1
decode2
decode3
decode4
decode0
decode1
decode2
decode3
decode4
op14
op14
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
op13
op13
0
op13
op13
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
result
result
en
C
clr
out
ovf
Counter
clk
A29
rRAMaddress
A30
rRAMoverflow
0-3
4-7
0-7
0
rRAMoverflow
1
1
1
1
A30
output
output
rRAMaddress
A31
valid
operand
0-7
0-3
4-7
operand[3:0]
operand[7:4]
selC
0-13
0-7
8-13
0-3
4-7
0-7
0-3
4-7
0-7
0
0
A1
0
0
0
0
1
A21
valid
A29
A30
A31
result
control-unit
rRAM-counter
nextstate-condition
op18
op19
=
op20
>
op21
<
op22
>
=
op23
<
=
jump-condition
selPC
A2
state
decoder
0
selpRAMaddress
operand
op15
selpRAMaddress
A
sel
D
ROM
accA
0-7
0-2
3-7
accB
0-7
0-2
3-7
0-2
3-5
0-5
1
AB
LCM
output
LCMa
D
C
en
Q
Reg
clk
LCMb
D
C
en
Q
Reg
clk
loadLCMa
loadLCMb
LCMa
LCMb
a
b
>
=
<
LCMa
LCMb
LCMfinish
0
0
LCMa
a
b
ci
s
co
Sub
LCM>
LCM<
LCMb
0
LCM>
LCMa
a
b
ci
s
co
Sub
LCMb
0
A20
A20
LCM<
A
D
C
en
Q
Reg
clk
B
D
C
en
Q
Reg
clk
a
b
LCMa
LCMb
0
0
A12
A19
a
b
mul
Mul
a
b
a
b
q
r
Div
LCMa
0-15
0-7
8-15
LCM1
LCM2
0-7
8-15
0-15
0
LCMfinish
0
reset
0x18
0
0
rRAMoverflow
rRAMoverflow
A24
A24
A24
A24
output
A12
A19
A
0
output
output
A12
A19
0-7
0-3
4-7
0-7
0-3
4-7
0-7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0-7
factorial
D
C
Q
Q
D
clk
D
C
Q
Q
D
clk
0
0
fact1state
fact0state
0
1
0,1
fact1state
fact0state
factcurrentstate
factcurrentstate
factcurrentstate
0
1
n
D
C
en
Q
Reg
clk
accA
0-7
0-2
3-7
0-2
3-7
0-7
0
0
factcurrentstate
f0
f1
f2
f3
A25
f0
f1
n
fact
D
C
en
Q
Reg
clk
f0
f1
0
f1
a
b
ci
s
co
Sub
n
1
0
a
b
mul
Mul
0-31
0-15
16-31
fact
n-1
n-1
n-1
fact
0
f0
a
b
>
=
<
n
2
n<=2
n<=2
n<=2
1
0
0
factloadrRAM
f2
f3
factloadrRAM
0
B
f3
0
A25
factoutput
factoutput
fact
0-15
0-7
8-15
0-7
8-15
0-15
0
0-7
8-15
0-15
0
0
f3
f3
f3
n
fact
D
C
Q
Q
D
clk
D
C
Q
Q
D
clk
0
0
max1state
max0state
0
1
0,1
max1state
max0state
maxcurrentstate
maxcurrentstate
maxcurrentstate
0
1
A26
1
0
0
max
index
D
C
en
Q
Reg
max
D
C
en
Q
Reg
clk
clk
0
0
maxcurrentstate
m0
m1
m2
m3
m0
accA
a
b
ci
s
co
Add
1
0
m0
m1
maxindex
maxindex
pRAM[maxindex]address
0
accA
m0
maxindex
a
b
>
=
<
pRAM[maxindex]
max
max
pRAM[maxindex]
0
pRAM[maxindex]address
A26
pRAM[maxindex]
0
A26
9
0
A26
max
maxindex
a
b
>
=
<
accB
index>accB
index>accB
index>accB
m3
m3
m3
m3
maxindex
max
A26
a
b
>
=
<
fact
0
0
1
0
0
0
0
0
0
A24
A24
A24
A24
A24
A24
A31
1
Test
01P01T01
Test
02P01T02
Test
03P02T01
Test
04P03T01
Test
05P03T02
Test
06P04T01
Test
07P05T01
Test
08P06T01
Test
09P06T02
Test
10P07T01
Test
11P07T02
Test
12P08T01
Test
13P08T02
Test
14P09T01
Test
15P09T02
Test
16P01T03
Test
17P02T02
Test
18P03T03
Test
19P04T02
Test
20P04T03
Test
26P10T01
Test
27P10T02
Test
28P11T01
Test
29P11T02
Test
21P05T2
Test
22P06T03
Test
23P07T03
Test
24P08T03
Test
25P09T03
Test
01P01T2
Test
02P01T3
Test
03P02T2
Test
04P03T2
Test
05P03T3
Test
06P04T2
Test
07P05T2
Test
08P06T2
Test
09P06T3
Test
10P07T2
Test
11P07T3
Test
12P08T2
Test
13P08T3
Test
14P09T2
Test
15P09T3